The History of Programmable Logic
By the
late 70’s, standard logic devices were the rage and printed circuit boards were
loaded with them. Then someone asked the question: “What if we gave the
designer the ability to implement different interconnections in a bigger
device?” This would allow the designer to integrate many standard logic devices
into one part. In order to give the ultimate in design flexibility Ron Cline
from Signetics (which was later purchased by Philips and then eventually XilinxÒ!) came up with the idea of two
programmable planes. The two programmable planes provided any combination of
‘AND’ and ‘OR’ gates and sharing of AND terms across multiple OR’s.
This architecture was very flexible, but at the time due to wafer geometry's of 10um the input to output delay or propagation delay (Tpd) was high which made the devices relatively slow.
MMI
(later purchased by AMD) was enlisted as a second source for the PLA array but
after fabrication issues was modified to become the Programmable Array Logic
(PAL) architecture by fixing one of the programmable planes. This new
architecture differs from that of the PLA by having one of the programmable
planes fixed - the OR array.
This PAL
architecture had the added benefit of faster Tpd and less complex software but
without the flexibility of the PLA structure. Other architectures followed,
such as the PLD (Programmable Logic Device). This category of devices is often
called Simple PLD (SPLD).
The
architecture has a mesh of horizontal and vertical interconnect tracks. At each
junction, there is a fuse. With the aid of software tools, the user can select
which junctions will not be connected by “blowing” all unwanted fuses. (This is
done by a device programmer or more commonly nowadays using In-System
Programming or ISP).Input pins are connected to the vertical interconnect and
the horizontal tracks are connected to AND-OR gates, also called “product
terms”. These in turn connect to dedicated flip-flops whose outputs are connected
to output pins.
PLDs
provided as much as 50 times more gates in a single package than discrete logic
devices! A huge improvement, not to mention fewer devices needed in inventory
and higher reliability over standard logic. Programmable Logic Device (PLD)
technology has moved on from the early days with such companies as Xilinx
producing ultra low power CMOS devices based on Flash technology. Flash PLDs
provide the ability to program the devices time and time again electrically
programming
and ERASING the device! Gone are the days of erasing taking in excess of twenty
minutes under an UV eraser.
Complex Programmable Logic Devices
(CPLDs)
Complex Programmable Logic Devices (CPLD) are another way to extend the density of the simple PLDs. The concept is to have a few PLD blocks or macrocells on a single device with general purpose interconnect in between. Simple logic paths can be implemented within a single block. More sophisticated logic will require multiple blocks and use the general purpose interconnect in between to make these connections.
CPLDs are great at handling wide and complex gating at blistering speeds e.g. 5ns which is equivalent to 200MHz. The timing model for CPLDs is easy to calculate so before you even start your design you can calculate your in to output speeds.
Field Programmable Gate Arrays
(FPGAs)
In 1985,
a company called Xilinx introduced a completely new idea. The concept was to
combine the user control and time to market of PLDs with the densities and cost
benefits of gate arrays. A lot of customers liked it - and the FPGA was born.
An FPGA
is a regular structure of logic cellsä or modules and interconnect which is
under the designer’s complete control. This means the user can design, program
and make changes to his circuit whenever he wants. And with FPGAs now exceeding
the 10 million gate limit the designer can dream big!
There are 2 basic types of FPGAs:
SRAM-based reprogrammable and One-time programmable (OTP). These two types of
FPGAs differ in the implementation of the logic cellä and the mechanism used to make
connections in the device.
The dominant type of FPGA is SRAM-based and can be reprogrammed by the user as often as the user chooses. In fact, an SRAM FPGA is reprogrammed every time it is powered-up because the FPGA is really a fancy memory chip! (That’s why you need a serial PROM or system memory with every SRAM FPGA).
In the
SRAM logic cell, instead of conventional gates there is instead a Look Up Table
(LUT) which determines the output based on the values of the inputs. SRAM bits
are also used to make connections.
One-time
programmable (OTP) FPGAs use anti-fuses (contrary to fuses, connections are
made not “blown” during programming) to make permanent connections in the chip
and so do not require a SPROM or other means to download the program to the
FPGA. However, every time you make a design change, you must throw away the
chip! The OTP logic cell is very similar to PLDs with dedicated gates and
flipflops.
References:
Programmable
Logic Design Quick Start Hand Book second edition –chapter one.
Mohammad Taha Etayeb.
CSDAlex4
etayebm@islamway.net