ardware description languages (HDLs) are used to describe the architecture and behavior of discrete electronic systems. HDLs were developed to deal with increasingly complex designs. An analogy is often made to the development of software description languages; from machine code (transistors and solder) to assembly language (netlists) to high-level languages (HDLs).

The idea is to use a high-level language to describe the circuit in a text file rather than a graphical low-level gate description. The term Behavioral could be used because in this powerful language, the designer describes the function or behavior of the circuit in words rather than figuring out the appropriate gates needed to create the application.

Top-down, HDL-based system design is most useful in large projects, where several designers or teams of designers are working concurrently. HDLs provide structured development. After major architectural decisions have been made and major components and their connections have been identified, work can proceed independently on subprojects.

There are two major flavors of HDL: VHDL and Verilog.

Advantages of HDLs

A design methodology that uses HDLs has several fundamental advantages over a traditional gate-level design methodology. Some of the advantages are listed below.

• You can verify design functionality early in the design process and immediately simulate a design written as an HDL description. Design simulation at this higher level, before implementation at the gate level, allows you to test architectural and design decisions.

• HDL descriptions supply technology-independent documentation of a design and its functionality. An HDL description is more easily read and understood than a netlist or schematic description. Because the initial HDL design description is technology-independent, you can later reuse it to generate the design in a different technology, without having to translate from the original technology.

• VHDL, like most high-level software languages, provides strong type checking.

A component that expects a four-bit-wide signal type cannot be connected to a three- or five-bit-wide signal; this mismatch causes an error when the HDL description is compiled. If a variable’s

range is defined as 1 to 15, an error results from assigning it a value of 0. Incorrectly using types is a major source of errors in descriptions. Type checking catches this kind of error in the HDL description even before a design is generated.

VHDL

The United States Department of Defense, as part of its Very High Speed Integrated Circuit (VHSIC) program, developed VHSIC High-level Design Language (VHDL) in 1982. VHDL describes the behavior, function, inputs, and outputs of a digital circuit design. VHDL is similar in style and syntax to modern programming languages, but includes many hardware-specific constructs.

VHDL is one of a few HDLs in widespread use today. VHDL is recognized as a standard HDL by the Institute of Electrical and Electronics Engineers (IEEE Standard 1076, ratified in 1987) and by the United States Department of Defense (MIL-STD-454L).

VHDL divides entities (components, circuits, or systems) into an external or visible part (entity name and connections) and an internal or hidden part (entity algorithm and implementation). After you define the external interface to an entity, other entities can use that entity when they all are being developed. This concept of internal and external views is central to a VHDL view of system design. An entity is defined, relative to other entities, by its connections and behavior. You can explore alternate implementations (architectures) of an entity without changing the rest of the design. After you define an entity for one design, you can reuse it in other designs as needed. You can develop libraries of entities to use with many designs or a family of designs.

As an example we will design a 16 by 16 multiplier. A multiplier is a regular but complex arrangement of adders and registers that requires quite a few gates. Our example has two 16 bit inputs (A and B) and a 32 bit product output (Y=A*B) - that’s a total of 64 I/Os. This circuit requires approximately 6,000 equivalent gates.

In the schematic implementation, all the required gates would have to be loaded, positioned on the page, interconnected, and I/O buffers added. About 3 days worth of work and 30 schematic page!!!!

The HDL implementation, which is also 6,000 gates, requires 8 lines of text and can be done in 3 minutes.

entity MULT is

port(A,B:in std_logic(15 downto 0);

Y:out std_logic(31 downto 0));

end MULT;

architecture BEHAVE of MULT is

begin

Y <= A * B;

end BEHAVE;

In addition to the tremendous time savings, the HDL method is completely vendor independent. That means that this same code could be used to implement a Xilinx FPGA as an LSI Logic gate array! This opens up tremendous design possibilities for engineers.

For example, what if you wanted to create a 32X32 multiplier.

Obviously, you would want to modify the work already done for the smaller multiplier. For the schematic approach, this would entail making 3 copies of the 30 pages, then figuring out where to edit the 90 pages so that they addressed the larger bus widths. This would probably require 4 hours of graphical editing. For the HDL specification, it would be a matter of changing the bus references: change 15 to 31 in line 2 and 31 to 63 in line 3 (4 seconds)!

entity MULT is

port(A,B:in std_logic(31 downto 0);

Y:out std_logic(63 downto 0));

end MULT;

architecture BEHAVE of MULT is

begin

Y <= A * B;

end BEHAVE;

Done!!!!!

So, as a designer, which method would you choose?

References:

1- Programmable Logic Design Quick Start Hand Book second edition –chapter One.

2- VHDL reference guide –chapter One.

3- Verilog reference manual version 1999.05 –chapter One.

4- Synthesis and Simulation Design Guide –chapter One.

Mohammad Taha Etayeb

CSDAlex4

etayebm@islamway.net